1. Technical Field
The present invention relates to network interfacing and more particularly, to methods and systems for buffering data between a host bus interface and a media access controller accessing Ethernet (IEEE 802.3) media.
2. Background Art
Network interface devices handle packets of data for transmission between a host computer and a network communications system, such as a local area network. The host computer may be implemented as a client station, a server, or a switched hub. One primary function of the network interface device is to buffer data to compensate for timing discrepancies between the clock domain of the host computer and the clock domain of the network.
Network interface devices typically include a first in, first out (FIFO) buffer memory for storing transmit and receive data, where the transmit data is stored in a transmit FIFO prior to transmission on the network media by the MAC, and receive data is stored in a receive FIFO by the MAC prior to transfer to the host computer via the host computer bus interface.
One disadvantage with the use of a FIFO for a transmit buffer or a receive buffer is the increased latency encountered during the buffering process. The latency of the network interface device is the time delay between the time that a data frame is supplied to the network interface device and the time the data is transmitted on the network media, or vice versa.
An additional disadvantage with the use of a FIFO for transmit buffer or receive buffer is the increasing complexity associated with maintaining status information for each data frame stored in the FIFO buffer. If a stored data frame is to have corresponding status information, then an additional FIFO buffer would be required for storing the status information for each stored data frame. Hence, a transmit buffer may require a data frame FIFO for the actual frame data, and a status FIFO for storing the corresponding status information for each data frame. Such an arrangement would result in a substantial increase in the amount of area required on a chip for the status FIFO. In addition, additional synchronization logic would be required to maintain correspondence between the stored frame data and the corresponding status data, increasing the cost and complexity of the network interface device.
An additional problem caused by the buffering of data between the clock domain of the host computer and the clock domain of the network interface device is buffer overflow or underflow. For example, buffer overflow can occur when the time domains between the host bus and the network media are uncontrollable to the extent that data is stored in the buffer at a rate faster than the data can be removed, resulting in an overflow situation. Conversely, underflow occurs if data is removed from the FIFO buffer faster than the data can be supplied.
Hence, the non-synchronous relationship between the host bus clock domain and the network clock domain have required the necessity of FIFO buffers to compensate for timing discrepancies between the host computer and the network.
Another fundamental problem with use of a FIFO as a transmit buffer or receive buffer is that there is no convenient way for the network interface device to bypass, or "flush," invalid data. For example, if the media access controller receives a runt packet from the network (i.e., an invalid packet less than the minimum required frame size of 64 bytes), the MAC cannot cause the invalid data stored in the FIFO to be flushed, without eliminating the entire contents of the receive FIFO. Hence, the invalid data is transferred via the host computer bus and stored in host computer memory, before the host computer can determine that the transferred data is invalid. The reduction in throughput may have substantial effects, especially in full-duplex networks, where the host computer bus is heavily utilized by the network interface device for simultaneous transmission and reception of data frames on the network medium.
An additional problem encountered with conventional network interface devices is the latency encountered during host bus transfers. In particular, two types of bus transfers may be used, namely master mode and slave mode. In master mode, the network interface device operates as a master, and initiates the transfer of data across the host bus by requesting use of the bus, and then transferring the data as a data burst. One example of a host bus is the peripheral component interconnect (PCI) local bus, where a transfer of data over a PCI bus includes an address phase followed by one or more contiguous data phases. The PCI bus protocol makes use of a centralized, synchronous arbitration scheme in which each PCI master must arbitrate for each transaction by use of a request signal and a grant signal. For example, a network interface device having data to transfer (e.g., either receive data or transmit data) will assert a request signal to request use of the bus. Typically, a host CPU will respond with a grant signal which is followed by assertion of a frame signal that together identify when the bus is available for use by the network interface.
One problem in conventional network interface devices is the occurrence of wait states following an address phase on the PCI bus. Such wait states cause increased latency on the PCI bus, further reducing the overall throughput of the network interface device.
An additional problem with conventional network interface devices is the occurrence of wait states encountered during a complex bus termination condition, where certain events on the PCI bus forcibly halt a PCI bus data transfer. Two examples of complex conditions include when a host memory is not ready to receive a data transfer after the bus has been secured, or when the host memory becomes unable to continue receiving data following initiation of the data transfer. In either case, the target asserts a STOP# signal on the PCI bus to terminate the data transfer. Prior art systems frequently lose data from the FIFO buffer memory in response to encountering such complex conditions, for example retry or disconnect states. Hence, complicated recovery arrangements are conventionally required in prior art systems to mitigate the loss of data. For example, higher network protocol layers may need to send a message across the network, requesting the transmitting station to resend a data packet.